FPGA RTL DESIGN AND SYSTEM VERILOG FOR VERIFICATION QUICK GUIDE: December 2019

hi, all this project is based on the Sobel edge detection algorithm which helps to reject the edge or corner of the video source.

the tool used: vivado 2018.3

implemented board : Zybo

video resolution : 720p60

purpose of this project: to develop a project which detects the edge of the video

1. block design of the project

2. dvi2rgb configuration

clocking wizard should be used pll which give the reference clock of 200 MHz to the dvi2rgb ip

i have used the Sobel edge detection IP provided by the digitronix Nepal.

constraints file ;

## This file is a general .xdc for the ZYBO Rev B board

## To use it in a project:

## - uncomment the lines corresponding to used pins

## - rename the used signals according to the project

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -of_objects [get_ports sys_clock]]

##Clock signal

set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L11P_T1_SRCC_35 Sch=sysclk

#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }];

##Switches

#IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B

##HDMI Signals

set_property -dict {PACKAGE_PIN H17 IOSTANDARD TMDS_33} [get_ports hdmi_clk_n]

set_property -dict {PACKAGE_PIN H16 IOSTANDARD TMDS_33} [get_ports hdmi_clk_p]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[0]}]

set_property PACKAGE_PIN D19 [get_ports {hdmi_in_d_p[0]}]

set_property PACKAGE_PIN D20 [get_ports {hdmi_d_n[0]}]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[0]}]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[1]}]

set_property PACKAGE_PIN C20 [get_ports {hdmi_d_p[1]}]

set_property PACKAGE_PIN B20 [get_ports {hdmi_d_n[1]}]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[1]}]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[2]}]

set_property PACKAGE_PIN B19 [get_ports {hdmi_d_p[2]}]

set_property PACKAGE_PIN A20 [get_ports {hdmi_d_n[2]}]

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[2]}]

#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC

set_property PACKAGE_PIN E18 [get_ports {hdmi_hpd[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_hpd[0]}]

#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN

set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_scl_io]

set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_sda_io]

##Pmod Header JA (XADC)

#set_

##VGA Connector

set_property PACKAGE_PIN M19 [get_ports {vga_pRed[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[0]}]

set_property PACKAGE_PIN L20 [get_ports {vga_pRed[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[1]}]

set_property PACKAGE_PIN J20 [get_ports {vga_pRed[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[2]}]

set_property PACKAGE_PIN G20 [get_ports {vga_pRed[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[3]}]

set_property PACKAGE_PIN F19 [get_ports {vga_pRed[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[4]}]

set_property PACKAGE_PIN H18 [get_ports {vga_pGreen_0[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[0]}]

set_property PACKAGE_PIN N20 [get_ports {vga_pGreen_0[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[1]}]

set_property PACKAGE_PIN L19 [get_ports {vga_pGreen_0[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[2]}]

set_property PACKAGE_PIN J19 [get_ports {vga_pGreen_0[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[3]}]

set_property PACKAGE_PIN H20 [get_ports {vga_pGreen_0[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[4]}]

set_property PACKAGE_PIN F20 [get_ports {vga_pGreen_0[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[5]}]

set_property PACKAGE_PIN P20 [get_ports {vga_pBlue_0[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[0]}]

set_property PACKAGE_PIN M20 [get_ports {vga_pBlue_0[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[1]}]

set_property PACKAGE_PIN K19 [get_ports {vga_pBlue_0[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[2]}]

set_property PACKAGE_PIN J18 [get_ports {vga_pBlue_0[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[3]}]

set_property PACKAGE_PIN G19 [get_ports {vga_pBlue_0[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[4]}]

set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports vga_pHSync_0]

set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports vga_pVSync_0]

#create_clock -period 9.259 -name hdmi_in_clk_p -waveform {0.000 4.629} [get_ports hdmi_clk_p]

#create_clock -period 8.334 -name hdmi_clk_pin -waveform {0.000 4.167} -add [get_ports hdmi_clk_p] ########working 119.9 mhz

create_clock -period 6.734 -name hdmi_clk_pin -waveform {0.000 3.367} -add [get_ports hdmi_clk_p] ########working 148.5 mhz

you can find the file on my GitHub project

https://github.com/arunchaudhary123/sobel-edge-detection-720p60-on-zybo

BLOCK DESIGN TPG_VTC_720P60 ZYBO

steps to of the project :

1. ADD IP
ZYNQ PROCESSING SYSTEM
CLOCKING WIZARD
VIDEO TEXT PATTERN GENERATOR
VIDEO TIMING CONTROLLER
AXI STREAM TO VIDEO OUT
CONSTANT
SLICER

2. PROJECT WAS CREATED AND TESTED ON VIVADO 2018.3 ON ZYBO BOARD YOU CAN USE ZEDBOARD AS WELL BUT YOU NEED TO CHANGE THE CONSTRAINTS FILE

3.CONSTRAINTS FILE FOR ZYBO

set_property PACKAGE_PIN L16 [get_ports sys_clock]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clock]

#create_clock -period 13.468 -waveform {0.000 5.000} [get_ports hdmi_clk_p] //// for 720p60 clock

set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_n]

##IO_L13P_T2_MRCC_35
set_property PACKAGE_PIN H16 [get_ports hdmi_clk_p]
set_property PACKAGE_PIN H17 [get_ports hdmi_clk_n]
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p]

#create_clock -period 6.756 -name hdmi_clk_pin -waveform {0.000 3.378} -add [get_ports hdmi_clk_p] #### 148 mhz
#create_clock -add -name hdmi_clk_pin -period 13.00 -waveform {0 6.5} [ get_ports hdmi_clk_p] ##### 74 megaherz frequency
create_clock -period 8.334 -name hdmi_clk_pin -waveform {0.000 4.167} -add [get_ports hdmi_clk_p] ########working 119.9 mhz
#create_clock -period 6.734 -name hdmi_clk_pin -waveform {0.000 3.367} -add [get_ports hdmi_clk_p] ########working 148.5 mhz

#create_clock -period 6.734 -waveform {0.000 3.367} -add [get_ports hdmi_clk_p] ###148.5 MHZ

set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[0]}]

##IO_L4P_T0_35
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[0]}]

##IO_L1N_T0_AD0N_35
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[1]}]

##IO_L1P_T0_AD0P_35
set_property PACKAGE_PIN D20 [get_ports {hdmi_d_p[1]}]
set_property PACKAGE_PIN B20 [get_ports {hdmi_d_n[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[1]}]

##IO_L2N_T0_AD8N_35
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[2]}]

##IO_L2P_T0_AD8P_35
set_property PACKAGE_PIN B19 [get_ports {hdmi_d_p[2]}]
set_property PACKAGE_PIN A20 [get_ports {hdmi_d_n[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[2]}]

##IO_L5N_T0_AD9N_35
#set_property PACKAGE_PIN E19 [get_ports hdmi_cec]
#set_property IOSTANDARD LVCMOS33 [get_ports hdmi_cec]

##IO_L5P_T0_AD9P_35
set_property PACKAGE_PIN E18 [get_ports {hdmi_hpd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_hpd[0]}]

##IO_L6N_T0_VREF_35
set_property PACKAGE_PIN F17 [get_ports {hdmi_out_en[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_out_en[0]}]

##IO_L16P_T2_35
set_property PACKAGE_PIN G17 [get_ports hdmi_in_ddc_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_in_ddc_scl_io]

##IO_L16N_T2_35
set_property PACKAGE_PIN G18 [get_ports hdmi_in_ddc_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports hdmi_in_ddc_sda_io]

set_property PACKAGE_PIN M19 [get_ports {vga_r[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}]

##IO_L9N_T1_DQS_AD3N_35
set_property PACKAGE_PIN L20 [get_ports {vga_r[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}]

##IO_L17P_T2_AD5P_35
set_property PACKAGE_PIN J20 [get_ports {vga_r[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}]

##IO_L18N_T2_AD13N_35
set_property PACKAGE_PIN G20 [get_ports {vga_r[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}]

##IO_L15P_T2_DQS_AD12P_35
set_property PACKAGE_PIN F19 [get_ports {vga_r[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[4]}]

##IO_L14N_T2_AD4N_SRCC_35
set_property PACKAGE_PIN H18 [get_ports {vga_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}]

##IO_L14P_T2_SRCC_34
set_property PACKAGE_PIN N20 [get_ports {vga_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}]

##IO_L9P_T1_DQS_AD3P_35
set_property PACKAGE_PIN L19 [get_ports {vga_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}]

##IO_L10N_T1_AD11N_35
set_property PACKAGE_PIN J19 [get_ports {vga_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}]

##IO_L17N_T2_AD5N_35
set_property PACKAGE_PIN H20 [get_ports {vga_g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[4]}]

##IO_L15N_T2_DQS_AD12N_35
set_property PACKAGE_PIN F20 [get_ports {vga_g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[5]}]

##IO_L14N_T2_SRCC_34
set_property PACKAGE_PIN P20 [get_ports {vga_b[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}]

##IO_L7N_T1_AD2N_35
set_property PACKAGE_PIN M20 [get_ports {vga_b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}]

##IO_L10P_T1_AD11P_35
set_property PACKAGE_PIN K19 [get_ports {vga_b[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}]

##IO_L14P_T2_AD4P_SRCC_35
set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}]

##IO_L18P_T2_AD13P_35
set_property PACKAGE_PIN G19 [get_ports {vga_b[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[4]}]

##IO_L13N_T2_MRCC_34
set_property PACKAGE_PIN P19 [get_ports vga_hs]
set_property IOSTANDARD LVCMOS33 [get_ports vga_hs]

##IO_0_34
set_property PACKAGE_PIN R19 [get_ports vga_vs]
set_property IOSTANDARD LVCMOS33 [get_ports vga_vs]

set_property PACKAGE_PIN G18 [get_ports DDC_sda_io]
set_property PACKAGE_PIN G17 [get_ports DDC_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports DDC_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports DDC_scl_io]

set_property PACKAGE_PIN G18 [get_ports ddc_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports ddc_sda_io]
set_property PACKAGE_PIN G17 [get_ports ddc_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports ddc_scl_io]

set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[0]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[2]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[5]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[19]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[22]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[6]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[7]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[11]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[12]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[18]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[1]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[3]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[13]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[16]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[20]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[21]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[4]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[8]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[9]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[10]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[14]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[15]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[17]}]
set_property MARK_DEBUG true [get_nets {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[23]}]
set_property MARK_DEBUG true [get_nets vga_test_i/v_axi4s_vid_out_0/vid_io_out_ce]
set_property MARK_DEBUG true [get_nets vga_test_i/v_axi4s_vid_out_0/vid_vsync]
set_property MARK_DEBUG true [get_nets vga_test_i/v_axi4s_vid_out_0/vid_active_video]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list vga_test_i/clk_wiz_0/inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 24 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[0]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[1]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[2]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[3]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[4]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[5]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[6]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[7]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[8]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[9]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[10]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[11]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[12]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[13]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[14]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[15]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[16]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[17]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[18]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[19]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[20]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[21]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[22]} {vga_test_i/v_axi4s_vid_out_0/s_axis_video_tdata[23]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list vga_test_i/v_axi4s_vid_out_0/vid_active_video]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list vga_test_i/v_axi4s_vid_out_0/vid_io_out_ce]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list vga_test_i/v_axi4s_vid_out_0/vid_vsync]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1]

4. MAKE THE SIMPLE HELLO WORLD APPLICATION PROJECT ON SDK AND REPLACE SOURCE MAIN.C FILE TO FOLLOWING SDK APPLICATION CODE FOR THE TPG CONFIGURATION

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/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
//
//#include <stdio.h>
//#include "platform.h"
//#include "xil_printf.h"

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
//#include "xvtc.h"
#include "xv_tpg.h"
#include "sleep.h"

/************************** Constant Definitions *****************************/

/** The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
//#define XVTC_DEVICE_ID XPAR_VTC_0_DEVICE_ID

#define XTPG_DEVICE_ID XPAR_V_TPG_0_DEVICE_ID

/************************** Variable Definitions *****************************/

//XVtc VtcInst; /**< Instance of the VTC core. */
XV_tpg xTpg;
//XV_tpg
u16 Offset;
u8 wr_reg =0;

u32 u32Read_value =0;

//int XVtc_SelfTest(XVtc *InstancePtr);
//int ConFig_Vtc_4_4k(XVtc *pVtc, u16 offset , u8 value);
int Intialise_TPG();
int Write_Configure_VTP_IP(XV_tpg *pxTpg, u16 OffsetAddress, u8 data_value);

int main()
{
init_platform();
int Status;
//XVtc_Config *Config;

/* Initialize the VTC driver so that it's ready to use look up
* configuration in the config table, then initialize it.
*/
//Config = XVtc_LookupConfig(XVTC_DEVICE_ID);

/* Checking Config variable */
//if (NULL == Config) {
// return (XST_FAILURE);
//}

//Status = XVtc_CfgInitialize(&VtcInst, Config, Config->BaseAddress);

/* Checking status */
//if (Status != (XST_SUCCESS)) {
// return (XST_FAILURE);
//}
//Status = XVtc_SelfTest(&VtcInst);
//if(Status != XST_SUCCESS){

// xil_printf("Error in Intialisation of VTC \r\n");
// return 0;
//}

//ConFig_Vtc_4_4k(&VtcInst, Offset , wr_reg);

Status = Intialise_TPG();
if(Status )
{
return XST_FAILURE;
}
//Status = Write_Configure_VTP_IP(&xTpg, XV_TPG_CTRL_ADDR_AP_CTRL, u8 data_value);
XV_tpg_Start(&xTpg);
Status=1;
while(Status){
Status = XV_tpg_IsReady(&xTpg);
xil_printf(" %x \r\n", Status);
usleep(100);
Status =0;
}
// XV_tpg_Set_width(&xTpg, 1920);
// XV_tpg_Set_height(&xTpg, 1080);
XV_tpg_Set_width(&xTpg, 1280);
XV_tpg_Set_height(&xTpg, 720);
// XV_tpg_Set_width(&xTpg, 3840);
// XV_tpg_Set_height(&xTpg, 2160);

u32Read_value = XV_tpg_Get_height(&xTpg);
xil_printf("%u \r\n", u32Read_value);
// 0x09 - is for Color-Bar Pattern
XV_tpg_Set_bckgndId(&xTpg, 0x09);
XV_tpg_EnableAutoRestart(&xTpg);
print("Hello World\n\r");
while(1){

print("Hello World\n\r");
sleep(1);
}
cleanup_platform();
return 0;
}

int Intialise_TPG()
{
int status =0;
XV_tpg_Config *Config;

Config = XV_tpg_LookupConfig(XTPG_DEVICE_ID);

if(Config ==NULL)
{

return(XST_FAILURE);
}
status = XV_tpg_CfgInitialize(&xTpg ,
Config,
Config->BaseAddress);
if(status !=XST_SUCCESS)
{
return XST_FAILURE;
}

return 0;
}

int Write_Configure_VTP_IP(XV_tpg *pxTpg, u16 OffsetAddress, u8 data_value)
{
int Status =0;
return Status ;
}

#if SAMPLE_VTC
/*****************************************************************************/
/**
*
* This function reads version register of the VTC core and compares with zero
* as part of self test.
*
* @param InstancePtr is a pointer to the XVtc instance.
*
* @return
* - XST_SUCCESS if the Version register read test was successful.
* - XST_FAILURE if the Version register read test failed.
*
* @note None.
*
******************************************************************************/
int XVtc_SelfTest(XVtc *InstancePtr)
{
u32 Version;
int Status;

/* Verify argument. */
Xil_AssertNonvoid(InstancePtr != NULL);

/* Read VTC core version register. */
Version = XVtc_ReadReg((InstancePtr)->Config.BaseAddress,
(XVTC_VER_OFFSET));

/* Compare version with zero */
if(Version != (u32)0x0) {
Status = (u32)(XST_SUCCESS);
}
else {
Status = (u32)(XST_FAILURE);
}

return Status;
}

/*
* ******************************************************
*
*
** *****************************************************
* */
int ConFig_Vtc_4_4k(XVtc *pVtc, u16 offset , u8 value)
{

Xil_AssertNonvoid(pVtc !=NULL);

XVtc_WriteReg((pVtc)->Config.BaseAddress,offset, value);

return 0;
}
#endif
/**

* End of File
*
*
* @}
*
*
* */

5. FOR THE 720P60 MAKE SURE CLOCKING WIZARD SHOULD BE MMCM AND SET OUTPUT FREQUENCY TO 74.25 AND FOR 1080P60 MAKE OUTPUT FREQUENCY TO 148.5 MHZ

6. VTC ALSO CONFIGURE ACCORDING TO YOUR REQUIRED RESOLUTION

7. VIDEO DEMONSTRATION
video link

https://www.youtube.com/watch?v=gQ54ZOEqI5g&feature=youtu.be

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