hi, all this project is based on the Sobel edge detection algorithm which helps to reject the edge or corner of the video source.
the tool used: vivado 2018.3
implemented board : Zybo
video resolution : 720p60
purpose of this project: to develop a project which detects the edge of the video
1. block design of the project
2. dvi2rgb configuration
clocking wizard should be used pll which give the reference clock of 200 MHz to the dvi2rgb ip
i have used the Sobel edge detection IP provided by the digitronix Nepal.
constraints file ;
## This file is a general .xdc for the ZYBO Rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -of_objects [get_ports sys_clock]]
##Clock signal
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }];
##Switches
#IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
##HDMI Signals
set_property -dict {PACKAGE_PIN H17 IOSTANDARD TMDS_33} [get_ports hdmi_clk_n]
set_property -dict {PACKAGE_PIN H16 IOSTANDARD TMDS_33} [get_ports hdmi_clk_p]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[0]}]
set_property PACKAGE_PIN D19 [get_ports {hdmi_in_d_p[0]}]
set_property PACKAGE_PIN D20 [get_ports {hdmi_d_n[0]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[0]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[1]}]
set_property PACKAGE_PIN C20 [get_ports {hdmi_d_p[1]}]
set_property PACKAGE_PIN B20 [get_ports {hdmi_d_n[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_n[2]}]
set_property PACKAGE_PIN B19 [get_ports {hdmi_d_p[2]}]
set_property PACKAGE_PIN A20 [get_ports {hdmi_d_n[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_d_p[2]}]
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
set_property PACKAGE_PIN E18 [get_ports {hdmi_hpd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_hpd[0]}]
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_scl_io]
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_sda_io]
##Pmod Header JA (XADC)
#set_
##VGA Connector
set_property PACKAGE_PIN M19 [get_ports {vga_pRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[0]}]
set_property PACKAGE_PIN L20 [get_ports {vga_pRed[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[1]}]
set_property PACKAGE_PIN J20 [get_ports {vga_pRed[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[2]}]
set_property PACKAGE_PIN G20 [get_ports {vga_pRed[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[3]}]
set_property PACKAGE_PIN F19 [get_ports {vga_pRed[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pRed[4]}]
set_property PACKAGE_PIN H18 [get_ports {vga_pGreen_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[0]}]
set_property PACKAGE_PIN N20 [get_ports {vga_pGreen_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[1]}]
set_property PACKAGE_PIN L19 [get_ports {vga_pGreen_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[2]}]
set_property PACKAGE_PIN J19 [get_ports {vga_pGreen_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[3]}]
set_property PACKAGE_PIN H20 [get_ports {vga_pGreen_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[4]}]
set_property PACKAGE_PIN F20 [get_ports {vga_pGreen_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pGreen_0[5]}]
set_property PACKAGE_PIN P20 [get_ports {vga_pBlue_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[0]}]
set_property PACKAGE_PIN M20 [get_ports {vga_pBlue_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[1]}]
set_property PACKAGE_PIN K19 [get_ports {vga_pBlue_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[2]}]
set_property PACKAGE_PIN J18 [get_ports {vga_pBlue_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[3]}]
set_property PACKAGE_PIN G19 [get_ports {vga_pBlue_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_pBlue_0[4]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports vga_pHSync_0]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports vga_pVSync_0]
#create_clock -period 9.259 -name hdmi_in_clk_p -waveform {0.000 4.629} [get_ports hdmi_clk_p]
#create_clock -period 8.334 -name hdmi_clk_pin -waveform {0.000 4.167} -add [get_ports hdmi_clk_p] ########working 119.9 mhz
create_clock -period 6.734 -name hdmi_clk_pin -waveform {0.000 3.367} -add [get_ports hdmi_clk_p] ########working 148.5 mhz
you can find the file on my GitHub project
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