FUNCTION AND PROCEDURE IN VHDL-- VHDL SERIES (1)

 -----------------VHDL CODE FOR FUNCTION AND PROCEDURE -------------------

----------------- AUTHOR ER.ARUN CHAUDHARY  -------------------------------------

----------------- DATE - 7/26/2021----------------------------------------------------------

-----------------VHDL CODE SERIES (1) ---------------------------------------------------

----------------------------------------------------------------------------------

-- Company: AUJUS TECHNOLOGY PVT LTD

-- Engineer: ARUN CHAUDHARY

-- 

-- Create Date: 07/25/2021 11:53:57 PM

-- Design Name: FUNCTION AND PROCEDURE TEST

-- Module Name: procedure_test - Behavioral

-- Project Name: 

-- Target Devices: 

-- Tool Versions: VIVADO 18.3

-- Description: 

-- 

-- Dependencies: 

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

-- 

----------------FUNCTION AND PROCEDURE IN THE VHDL ------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use IEEE.NUMERIC_STD.ALL;

entity procedure_test is

   generic ( N : integer  :=4) ; 

    Port ( x : in STD_LOGIC_vector ( N-1 downto 0);

           y : in STD_LOGIC_vector( N-1 downto 0);

           sum : out STD_LOGIC_vector( N-1 DOWNTO 0) ;

           diff : out STD_LOGIC_VECTOR( N-1 DOWNTO 0);

            m: OUT std_logic_vector(N*2-1 DOWNTO 0) 

           );

end procedure_test;

architecture Behavioral of procedure_test is

---------------PROCEDURE AND FUNCTION BOTH HAVE THE DEFINTION WHILE WRITING PROTOTYPE 

---------------PROCEDURE CAN TAKE ANY NUMBER OF INPUT AND OUTPUT VARIABLE 

-------------- IN PROCEDURE WE DONT NEED TO DEFINE RETURN TYPE ------

procedure SumAndDiff( signal  a : IN STD_LOGIC_VECTOR( N-1 DOWNTO 0) ; 

                     SIGNAL  b : in std_logic_Vector( N-1 downto 0) ; 

                     signal sum :  out std_logic_vector( N-1 DOWNTO 0) ; 

                     SIGNAL DIFF:  OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0) )IS                   

begin

  sum <= a +b ; 

  diff <= a-b ;  

END  sumAndDiff ; 

---------------------IN FUNCTION WE CAN DEFINE ONLY INPUT VARIABLE 

--------------------IN FUNCTION WE NEED TO DEFINE RETURN TYPE 

-------------------FUNCTION RETURN VALUE ALWAYS 

function multiplication ( signal a : in std_logic_vector(N-1 DOWNTO 0) ; 

                         SIGNAL B: IN STD_LOGIC_VECTOR( N-1 DOWNTO 0)

                         ) return std_Logic_vector is 

                        VARIABLE  MULTI : STD_LOGIC_VECTOR( N*2-1 DOWNTO 0) ;              

BEGIN 

    multi := a * b ; 

   return multi ;       

END multiplication  ;                    

--------------------------------------------------------------------------

begin 

--------------WHILE CALLING THE  PROCEDURE WE NEED TO  CONNECT THE INPUT AND OUTPUT VARIABLE AS IN THE PORT MAPING 

   sumAndDIFF ( a=>x , b=>y , sum=>sum , diff=>diff) ; ------ procedure calling 

-------------WHILE CALLING THE FUNCTION WE NEED TO HAVE A VARIABLE WHICH WILL BE HOLDING RETURN VALUE 

   M<= multiplication (A=>X, B=>Y ) ; 

  

end Behavioral;

ELABORATED DESIGN: