--------------texas instrument v1.0
--------------------------------------------------------------------------------
-- Company: AUJUS TECHNOLOGY PRIVATE LIMITED
-- Engineer: ARUN CHAUDHARY
--
-- Create Date: 30.09.2020 11:08:56
-- Design Name: TEXAS INSTRUMENT ADC CONTROLLER
-- Module Name: ads8661_new_verison - Behavioral
-- Project Name: TIMMING DISSIMINATION
-- Target Devices: ZEDBOARD
-- Tool Versions: VIVADO 2018.3
-- Description:
--
-- Dependencies:
--
-- Revision:VERSION V1.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
entity ads8661_new_verison is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sdo_from_adc : in STD_LOGIC;
rvs_from_adc : in STD_LOGIC;
convst_to_adc : out STD_LOGIC;
rstn_to_adc : out STD_LOGIC;
sdi_to_adc : out STD_LOGIC;
sclk_to_adc : out STD_LOGIC);
end ads8661_new_verison;
architecture Behavioral of ads8661_new_verison is
signal sclk_counter_reg , sclk_counter_Next : std_logic_vector ( 4 downto 0) ;
signal gen_clk : std_logic ;
signal sclk50_mhz : std_logic ;
signal shift32_reg_from_adc, shift32_next_from_adc : std_Logic_vector ( 31 downto 0) ;
signal shift32_reg_to_adc , shift32_next_to_adc , shift32_reg_to_adc1 , shift32_next_to_adc1: std_logic_Vector ( 31 downto 0) ;
type state is ( power_up ,acq,rst_state,acq0,frame0,conv0,
acq1, frame1, conv1 , acq2, frame2, conv2, acq3, frame3, conv3,
acq4, frame4, conv4,
acq5 , frame5,conv5 ,acq6 ,frame6 , conv6 , acq7 , frame7 , conv7 ,acq8 ) ;
signal state_reg , state_next : state ;
--------------------------commands --------for configuration of adc
-- constant nop :std_logic_vector(31 downto 0) := x"00000000" ;
-- constant clear_hword : std_logic_vector( 7 downto 0) :="11000XX0" ;
-- constant read_hword : std_logic_vector ( 7 downto 0) := "11001XX0" ;
-- constant READ: std_logic_vector ( 7 downto 0) :="01001XX0" ;
-- constant write_hword : std_logic_vector ( 7 downto 0) := "11010000" ;
constant write_MS : std_logic_vector ( 7 downto 0) := "11010010" ;
constant write_LS : std_logic_vector ( 7 downto 0) := "11010100" ;
-- constant SET_HWORD : std_logic_vector ( 7 downto 0) := "11011XX0";
-------------===========REGISTER ADDRESS -------------
-- constant DEVICE_ID_REG : std_logic_vector ( 7 downto 0) := x"00";
-- constant RST_PWRCTL_REG : std_logic_vector ( 7 downto 0) := x"04" ;
-- constant SDI_CTL_REG : std_logic_vector ( 7 downto 0) :=x"08" ;
-- constant SDO_CTL_REG : std_logic_vector ( 7 downto 0) :=x"0c" ;
-- constant DATAOUT_CTL_REG : std_logic_vector ( 7 downto 0) :=x"10" ;
-- constant RANGE_SEL_REG : std_logic_vector ( 7 downto 0) := x"14" ;
-- constant ALARM_REG : std_logic_vector ( 7 downto 0) :=x"20" ;
-- constant ALARM_H_TH_REG : std_logic_vector ( 7 downto 0) :=x"24" ;
-- constant ALARM_L_TH_REG : std_logic_vector( 7 downto 0) :=x"28" ;
constant wait_20ms : integer := 1999999 ; -----------20 ms ie . 20 ms *100 mhz -1 = 1999999 ;
----------------rst-pwrct-reg---------------------------
constant rst_ctl_wkey_addr : std_logic_vector (7 downto 0) :=x"05" ; ----- write x"69 " to this register to enable write in 5-0 bit of rst-pwrctl-reg
constant rst_write_addr : std_logic_vector (7 downto 0) :=x"04" ;
constant vdd_al_dis : std_logic :='0';
constant in_al_dis : std_logic :='0';
constant rstin_app : std_logic :='0';
constant nap_en : std_logic :='0';
constant pwrdn : std_logic :='0';
--------------=====================================
-------sdi-ctl-reg== 08h ========================
constant sdi_ctl_reg_addr : std_logic_vector ( 7 downto 0) :=x"08" ;
constant sdi_mode :std_logic_vector (1 downto 0) :="00" ; ------spi mode cpol=0 cphase=0
-----------------------------------------------------------------------------
----- sdo-ctl-reg---=====0ch =========================
constant sdo_ctl_reg_addr : std_logic_vector ( 7 downto 0) :=x"0C" ;
constant ssync_clk :std_logic :='0' ; --- 0 external clock 1- internal clock
constant sdo_mode :std_logic_vector(1 downto 0) :="0X" ; ---- follow same spi protocols that used for sdi mode
--------dataout control register ---- 11h
constant dataout_ctl_reg_addrms : std_logic_vector( 7 downto 0) :=x"11" ; --------------1st addr
constant device_addr_inc :std_logic :='0' ; --- 0 external clock 1- internal clock
constant vdd_active_alarm_inc :std_logic_vector (1 downto 0) :="11" ;
constant in_active_alarm_inc :std_logic_vector (1 downto 0) :="11" ;
constant range_inc :std_logic :='1' ;
constant dataout_ctl_reg_addrls : std_logic_vector ( 7 downto 0) :=x"10" ; ---------second addr ----------
constant par_en :std_logic :='0' ; --- 0 disable 1 enable
constant data_val :std_logic_vector (2 downto 0) :="0XX" ; ---------conversion data
-------------range selection register --- 14h
constant range_sel_addr : std_logic_vector ( 7 downto 0) :=x"14" ; --------
constant intref_dis:std_logic :='0' ; --- 0 disable 1 enable
constant range_sel:std_logic_vector(3 downto 0) :="0011" ; ---------range _+ 1.25*vref
------------------counter for delay ----------------
signal count_reg , count_next : std_logic_vector ( 20 downto 0) ;
type state2 is ( idle1, rst1_config,rst2_config , sdi_config , sdo_config , data_out_config1,
data_out_config2 , range_config ,adc_frame ,wait1,wait2,wait3,wait4,wait5,wait6,wait7,wait8,wait_new_frame ) ;
signal state_reg1, state_next1: state2 ;
signal rst_wkey_done ,rst_vdd_in_done ,sdi_done , sdo_done
, dataout_ms_done , dataout_ls_done ,range_done ,adc_frame_done : std_logic ;
signal shift_reg_to_adc : std_logic_vector ( 31 downto 0) ;
signal sdi_to_adc_Reg , sdi_to_adc_next : std_logic ;
signal shift_reg_sdi,shift_next_sdi , shift_reg_sdo , shift_next_sdo,shift_reg_dout, shift_next_dout ,
shift_reg_dout1, shift_reg_dconv, shift_next_dconv , shift_reg_range,shift_next_range : std_logic_vector(31 downto 0) ;
-----------------------==========================================
signal new_frame :std_logic ;
signal sdo_from_adc_reg : std_logic ;
signal state_change : std_logic ;
signal conv_done0, conv_done1 ,conv_done2,conv_done3,conv_done4,conv_done5,conv_done6,conv_done7,conv_done8,conve_done9 : std_logic ;
---------------------============================================
begin
--------------sclk generation --------------
-----top level port map
sdi_to_adc <= sdi_to_adc_Reg;
sclk_to_adc <=sclk50_mhz ;
process ( clk ,rst )
begin
if ( rst='1') then
sclk50_mhz <='0' ;
state_change <='0' ;
elsif rising_edge ( clk ) then
if ( gen_clk='1') then
state_change <='1' ;
sclk50_mhz <= not sclk50_mhz ;
else
sclk50_mhz <='0' ;
state_change<='0' ;
end if ;
end if ;
end process ;
----------------------------------------------state reg for 50 mhz clock
process ( sclk50_mhz , rst )
begin
if ( rst='1') then
state_reg1 <= idle1 ;
sdo_from_adc_reg <='0' ;
shift32_reg_to_adc<= ( others=>'0') ;
shift32_reg_to_adc1<= ( others=>'0') ;
shift_reg_sdi <= ( others=>'0') ;
shift_reg_sdo <= ( others=>'0') ;
shift_reg_dout <= ( others=>'0') ;
shift_reg_dconv <= (others=>'0') ;
shift_reg_range <= ( others=>'0') ;
shift32_reg_from_adc <=(others=>'0' ) ;
sclk_counter_reg <="00000" ;
sdi_to_adc_reg <='0' ;
elsif rising_Edge ( sclk50_mhz) then
state_reg1 <= state_next1 ;
sdo_from_adc_reg <= sdo_from_adc ;
shift32_Reg_to_adc <= shift32_next_to_adc ;
shift32_Reg_to_adc1 <= shift32_next_to_adc1 ;
shift_reg_sdi <= shift_next_sdi ;
shift_reg_sdo <= shift_next_sdo ;
shift_reg_dout <= shift_next_dout;
shift_reg_dconv <= shift_next_dconv ;
shift_reg_range <= shift_next_range ;
shift32_reg_from_adc <=shift32_next_from_adc;
sclk_counter_reg <= sclk_counter_next ;
sdi_to_adc_reg <=sdi_to_adc_next ;
end if ;
end process ;
----------------next state combinational logic
process ( shift32_reg_to_adc ,state_reg1 ,sclk_counter_reg,sdi_to_adc_reg,
shift32_reg_to_adc1, shift_reg_sdi, shift_reg_sdo , shift_reg_dout ,
shift_reg_range,shift_reg_dconv, shift32_reg_from_adc ,sdo_from_adc_reg,state_change,
conv_done7)
begin
--------------DEFAULT VALUE OF ALL THE REGISTERS
shift32_next_to_adc <= write_ms & rst_ctl_wkey_addr & x"6900" ;
shift32_next_to_adc1 <= write_ms & rst_write_addr & x"00" & "00" & vdd_al_dis & in_al_dis & '0' & rstin_app & nap_en & pwrdn ;
shift_next_sdi <= write_ls & sdi_ctl_reg_addr & x"00" & "000000" & sdi_mode ;
shift_next_sdo <= write_ls & sdo_ctl_reg_addr & x"00" & '0' & ssync_clk & "0000" & sdo_mode ;
shift_next_dout <= write_ms & dataout_ctl_reg_addrms & '0' & device_addr_inc & vdd_active_alarm_inc & in_active_alarm_inc & '0' & range_inc & x"00" ;
shift_next_dconv <= write_ls & dataout_ctl_reg_addrls & x"00" & "0000" & par_en & data_val ;
shift_next_range<= write_ls & range_sel_addr & x"00" & '0' & intref_dis & "00" & range_sel ;
shift32_next_from_adc <=shift32_reg_from_adc; ------- shift register to store data from adc
state_next1 <= state_reg1 ;
sclk_counter_next <= sclk_counter_reg ;
rst_wkey_done <='0' ;
rst_vdd_in_done<='0' ;
sdi_done <='0' ;
sdo_done <='0' ;
dataout_ms_done<='0' ;
dataout_ls_done <='0' ;
range_done <='0' ;
adc_frame_done <='0' ;
sdi_to_adc_next<=sdi_to_adc_reg ; ---------------serial configuration data to adc
case state_reg1 is
when idle1=>
if ( state_change='1') then
state_next1 <= rst1_config ;
end if ;
when rst1_config =>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift32_reg_to_adc(31) ;
shift32_next_to_adc <= shift32_reg_to_adc ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 ) then
sclk_counter_next <= "00000" ;
-- rst_wkey_done <='1' ;
-- state_next1 <= rst2_config ;
state_next1 <= wait1;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait1=>
rst_wkey_done <='1' ;
-- if ( conv_done0='1') then
state_next1 <= rst2_config;
-- state_next1 <= rst1_config;
-- end if ;
when rst2_config=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift32_reg_to_adc1(31) ;
shift32_next_to_adc1 <= shift32_reg_to_adc1 ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1') then
sclk_counter_next <= "00000" ;
-- rst_vdd_in_done<='1' ;
-- state_next1 <= sdi_config ;
state_next1 <= wait2 ;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait2=>
rst_vdd_in_done<='1' ;
-- if ( conv_done1='1') then
state_next1 <= sdi_config;
-- state_next1 <= rst1_config;
-- end if ;
when sdi_config=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift_reg_sdi(31) ;
shift_next_sdi <= shift_reg_sdi ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1') then
sclk_counter_next <= "00000" ;
-- sdi_done <='1' ;
-- state_next1 <= sdo_config ;
state_next1 <= wait3;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait3=>
-- if ( conv_done2='1') then
state_next1 <= sdo_config;
sdi_done <='1' ;
-- end if ;
when sdo_config=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift_reg_sdo(31) ;
shift_next_sdo <= shift_reg_sdo ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1' ) then
sclk_counter_next <= "00000" ;
-- sdo_done <='1' ;
-- state_next1 <= data_out_config1 ;
state_next1 <= wait4 ;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait4=>
-- if ( conv_done3='1') then
state_next1 <= data_out_config1;
sdo_done <='1' ;
-- end if ;
when data_out_config1=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift_reg_dout(31) ;
shift_next_dout <= shift_reg_dout ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1') then
sclk_counter_next <= "00000" ;
-- dataout_ms_done<='1' ;
-- state_next1 <= data_out_config2 ;
state_next1 <= wait5 ;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait5=>
-- if ( conv_done4='1') then
state_next1 <= data_out_config2;
dataout_ms_done<='1' ;
-- end if ;
when data_out_config2=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift_reg_dconv(31) ;
shift_next_dconv <= shift_reg_dconv ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1') then
sclk_counter_next <= "00000" ;
-- dataout_ls_done<='1' ;
-- state_next1 <= range_config ;
state_next1 <= wait6;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait6=>
-- if ( conv_done5='1') then
state_next1 <= range_config;
dataout_ls_done<='1' ;
-- end if ;
when range_config=>
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
sdi_to_adc_next <= shift_reg_range(31) ;
shift_next_range <= shift_reg_range ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 and state_change='1') then
sclk_counter_next <= "00000" ;
-- range_done<='1' ;
-- state_next1 <= adc_frame ;
state_next1 <= wait7 ;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait7=>
-- if ( conv_done6='1') then
state_next1 <= adc_frame;
range_done<='1' ;
-- end if ;
when adc_frame =>
adc_frame_done<='0' ;
shift32_next_from_adc <= shift32_reg_from_adc (30 downto 0) & sdo_from_adc_reg ;
-- sdi_to_adc_next <= shift_reg_range(31) ;
-- shift_next_range <= shift_reg_range ( 30 downto 0) & '0' ;
if ( sclk_counter_reg=31 ) then
sclk_counter_next <= "00000" ;
state_next1 <= wait8 ;
else
sclk_counter_next <= sclk_counter_reg +1 ;
end if ;
when wait8=>
-- if (conv_done7='1') then
-- adc_frame_done<='0' ;
adc_frame_done<='1' ;
state_next1 <=adc_frame ;
-- end if ;
when wait_new_frame =>
state_next1 <= adc_frame ;
adc_frame_done<='0' ;
end case ;
end process ;
---------======state_reg ---------------
process (clk ,rst )
begin
if ( rst ='1') then
state_reg <= power_up ;
count_reg <= (others=>'0') ;
elsif rising_edge (clk) then
state_reg <= state_next ;
count_reg <= count_next ;
end if ;
end process ;
-------------=====combinational state machine control
process ( state_reg , rvs_from_adc, count_reg,rst_wkey_done,rst_vdd_in_done, sdi_done,sdo_done, range_done, dataout_ms_done, dataout_ls_done, adc_frame_done)
begin
---------default value and default state declare
state_next <= state_reg ;
gen_clk <='0' ;
convst_to_adc<='0' ;
rstn_to_adc <='1' ;
count_next <= count_reg ;
new_frame <='0' ;
conv_done1 <='0' ;
conv_done2 <='0' ;
conv_done3 <='0' ;
conv_done4 <='0' ;
conv_done5 <='0' ;
conv_done6 <='0' ;
conv_done7 <='0' ;
conv_done8 <='0' ;
conv_done0 <='0' ;
case state_reg is
when power_up =>
state_next <= acq ;
when acq =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ;
state_next <= rst_state;
when rst_state =>
convst_to_adc<='1' ;
rstn_to_adc <='0' ;
-- if ( count_reg = wait_20ms ) then
-- count_next <= (others=>'0') ;
state_next <= acq0 ;
-- else
-- count_next <= count_reg +1 ;
-- end if ;
------------------------rst register write ---------------
when acq0 => ----- once clock cycles is 20 ns that is meet the minm requirement for setup time
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation we are waiting here 10 ns in this state
state_next <= frame0 ;
when frame0 =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( rst_wkey_done ='1') then
state_next <= conv0 ;
gen_clk <='0' ;
end if ;
when conv0 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq1 ;
-- state_next <=acq0 ;
conv_done0 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
--------------------------------------------------
when acq1 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame1 ;
when frame1 =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( rst_vdd_in_done='1') then
state_next <= conv1 ;
gen_clk <='0' ;
end if ;
when conv1 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq2 ;
-- state_next <=acq0 ;
conv_done1 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
-----------------------------------------------xxxxxxxxxxxxxxxxxxxx
------------------sdi data write ---------------------
when acq2 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame2 ;
when frame2 =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( sdi_done='1') then
state_next <= conv2 ;
gen_clk <='0' ;
end if ;
when conv2 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq3 ;
conv_done2 <='0' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
------------------------sdo data write -------------
when acq3 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame3 ;
when frame3 =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( sdo_done='1') then
state_next <= conv3 ;
gen_clk <='0' ;
end if ;
when conv3 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq4 ;
conv_done3 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
--------------data reg ms write -------------------------
when acq4 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame4 ;
when frame4=>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( dataout_ms_done='1') then
state_next <= conv4 ;
gen_clk <='0' ;
end if ;
when conv4 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq5 ;
conv_done4 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
------data reg ls write ----------------
when acq5 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame5 ;
when frame5 =>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( dataout_ls_done='1') then
state_next <= conv5 ;
gen_clk <='0' ;
end if ;
when conv5 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq6 ;
conv_done5 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
------range data write --------------------
when acq6 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame6 ;
when frame6=>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
if ( range_done='1') then
state_next <= conv6 ;
gen_clk <='0' ;
end if ;
when conv6 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq7 ;
conv_done6 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
-----------adc frame wirte -----------------
when acq7 => ----- once clock cycles is 20 ns that is meet the minm requirement
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='0' ; ------- wait for 7.5 ns minimum to enable clock generation
new_frame <='0' ;
state_next <= frame7 ;
when frame7=>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ;
new_frame <='1' ;
if ( adc_frame_done='1') then
state_next <= conv7 ;
gen_clk <='0' ;
new_frame <='0' ;
end if ;
when conv7 =>
convst_to_adc <='1' ;
rstn_to_adc <='1' ;
gen_clk<='0' ;
new_frame <='0' ;
if ( count_reg = 60 or rvs_from_adc='0' ) then
count_next <=(others=>'0') ;
state_next <=acq8 ;
conv_done7 <='1' ;
else
count_next <= count_reg +1 ;
if (count_reg >=2 and count_reg <=60) then
convst_to_adc <='1' ;
else
convst_to_adc <='0' ;
end if ;
end if ;
when acq8=>
convst_to_adc <= '0' ;
rstn_to_adc <='1' ;
gen_clk <='1' ; ------- wait for 7.5 ns minimum to enable clock generation
state_next <= frame7 ;
when others=>
convst_to_adc<='0' ;
rstn_to_adc<='1' ;
gen_clk <='1' ;
state_next <= frame7 ;
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end case ;
end process ;
end Behavioral;
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