zedboard -xadc instantiation working
configuration step :
1 .
2.
3.
4.
5.
synthesized schematic design :
xadc controller vhdl code :
----------------------------------------------------------------------------------
-- Company: aujus technology private limited
-- Engineer: arun chaudhary
--
-- Create Date: 08.10.2020 19:10:13
-- Design Name: xadc controller
-- Module Name: xacd_top - Behavioral
-- Project Name: timming dissimination
-- Target Devices: zedboard
-- Tool Versions: vivado 2018.3
-- Description: it takes the analog input signal from signal generator and produce a digital output
--
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments:
-- any changes will update here
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity xacd_top is
Port ( clk : in STD_LOGIC;
rst : in std_logic ;
adc_data : in std_logic_vector( 15 downto 0) ;
drdy : in std_logic ;
latch_data: in std_logic ;
addr : out std_logic_vector ( 6 downto 0) ;
digital_out : out STD_LOGIC_VECTOR (3 downto 0));
end xacd_top;
architecture Behavioral of xacd_top is
type state is ( wait1, read , wait2) ;
signal state_reg , state_next : state ;
signal data_reg , data_next : std_Logic_Vector( 15 downto 0) ;
signal eoc , eos , bsy , den : std_logic ;
signal addr_reg , addr_next : std_logic_Vector ( 7 downto 0) ;
signal chanel : std_logic_Vector ( 4 downto 0 ) ;
signal alarm : std_logic ;
signal ready_reg : std_logic ;
begin
process ( clk ,rst )
begin
if ( rst='1') then
data_reg <= ( others=>'0' ) ;
state_reg <= wait1 ;
addr_reg <= x"03" ;
elsif rising_Edge ( clk ) then
data_reg <= data_next ;
state_reg <= state_next ;
addr_reg <= addr_next ;
end if ;
end process ;
------------------
process ( data_reg , state_reg , addr_reg , latch_data,adc_data,drdy )
begin
state_next <= state_reg ;
data_next <= data_reg ;
addr_next <= addr_reg ;
case state_reg is
when wait1=>
addr_next <= x"03" ;
if ( latch_data='1' ) then
state_next <= read ;
end if ;
when read =>
addr_next <= x"03" ;
if ( drdy='1') then
data_next <= adc_data ;
end if ;
if ( latch_data='0' ) then
state_next <= wait2 ;
end if ;
when wait2=>
if ( latch_data='1') then
state_next <= wait1 ;
end if ;
when others=>
state_Next <= wait1 ;
end case ;
end process ;
digital_out <= data_reg ( 15 downto 12 ) ;
addr <= addr_reg(6 downto 0) ;
end Behavioral;
xadc -- top file ----
------------------------top file --------------------------------
---------clock wizard which takes 100 mhz and produce output 50 mhz signal which drive xadc and -- controller
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.10.2020 12:49:44
-- Design Name:
-- Module Name: top1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0);
en : in STD_LOGIC;
vp : in STD_LOGIC;
vn : in STD_LOGIC);
end top1;
architecture Behavioral of top1 is
signal drdy,den : std_logic ;
signal adc_data : std_logic_vector ( 15 downto 0) ;
signal addr : std_logic_vector( 6 downto 0) ;
signal bsy , alarm , eos : std_logic ;
signal channel : std_logic_vector ( 4 downto 0) ;
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
clk_in1 : in std_logic
);
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
component xacd_top is
Port ( clk : in STD_LOGIC;
rst : in std_logic ;
drdy : in std_logic ;
adc_data : in std_logic_vector( 15 downto 0) ;
addr : out std_logic_vector ( 6 downto 0) ;
-- vauxp6 : in STD_LOGIC;
latch_data: in std_logic ;
-- vauxn6 : in STD_LOGIC;
digital_out : out STD_LOGIC_VECTOR (3 downto 0));
end component xacd_top;
component xadc_wiz_1 is
port
(
daddr_in : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
den_in : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
di_in : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
dwe_in : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
do_out : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
drdy_out : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
dclk_in : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component ;
signal clk50 : std_logic ;
begin
your_instance_name : clk_wiz_0
port map (
-- Clock out ports
clk_out1 => clk50 ,
-- Clock in ports
clk_in1 => clk
);
u1 : xacd_top
Port map ( clk => clk50 , ------ : in STD_LOGIC;
rst=> rst , ----- : in std_logic ;
drdy => drdy , --------- : in std_logic ;
adc_data => adc_data , ------------: in std_logic_vector( 15 downto 0) ;
addr=> addr , ----- : out std_logic_vector ( 6 downto 0) ;
latch_data=> en , ----- : in std_logic ;
digital_out => dout ) ; --- : out STD_LOGIC_VECTOR (3 downto 0));
u2 : xadc_wiz_1
port map
(
daddr_in => addr(6 downto 0) ,
den_in => den , -- Enable Signal for the dynamic reconfiguration port
di_in => x"0000" , ---- : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
dwe_in => '0' , ---- : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
do_out => adc_data , --- : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
drdy_out => drdy , ------ : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
dclk_in => clk50 , ----- : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
-- vauxp6 => aux6p , ------ : in STD_LOGIC; -- Auxiliary Channel 6
-- vauxn6 => aux6n , ---- : in STD_LOGIC;
busy_out => bsy , ---- : out STD_LOGIC; -- ADC Busy signal
channel_out => channel , ---- out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out =>den , --- : out STD_LOGIC; -- End of Conversion Signal
eos_out => eos , -- : out STD_LOGIC; -- End of Sequence Signal
alarm_out => alarm , -- : out STD_LOGIC; -- OR'ed output of all the Alarms
vp_in => vp, --- : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in => vn -- : in STD_LOGIC
);
end Behavioral;
# file: xadc_wiz_1_exdes.xdc
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
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# special, incidental, or consequential loss or damage
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# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
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# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
create_clock -name dclk_in -period 10 [get_ports dclk_in]
set_property PACKAGE_PIN F22 [get_ports latch_data]
set_property PACKAGE_PIN F22 [get_ports rst]
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property MARK_DEBUG true [get_nets {adc_data[1]}]
set_property MARK_DEBUG true [get_nets {adc_data[10]}]
set_property MARK_DEBUG true [get_nets {adc_data[11]}]
set_property MARK_DEBUG true [get_nets {adc_data[15]}]
set_property MARK_DEBUG true [get_nets {adc_data[0]}]
set_property MARK_DEBUG true [get_nets {adc_data[6]}]
set_property MARK_DEBUG true [get_nets {adc_data[9]}]
set_property MARK_DEBUG true [get_nets {adc_data[12]}]
set_property MARK_DEBUG true [get_nets {adc_data[2]}]
set_property MARK_DEBUG true [get_nets {adc_data[7]}]
set_property MARK_DEBUG true [get_nets {adc_data[8]}]
set_property MARK_DEBUG true [get_nets {adc_data[3]}]
set_property MARK_DEBUG true [get_nets {adc_data[4]}]
set_property MARK_DEBUG true [get_nets {adc_data[5]}]
set_property MARK_DEBUG true [get_nets {adc_data[13]}]
set_property MARK_DEBUG true [get_nets {adc_data[14]}]
set_property MARK_DEBUG true [get_nets ready]
set_property MARK_DEBUG true [get_nets den]
set_property MARK_DEBUG true [get_nets u1/ready]
set_property PACKAGE_PIN M12 [get_ports vn]
set_property PACKAGE_PIN G22 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN U22 [get_ports {dout[0]}]
set_property PACKAGE_PIN U21 [get_ports {dout[1]}]
set_property PACKAGE_PIN T22 [get_ports {dout[2]}]
set_property PACKAGE_PIN T21 [get_ports {dout[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[0]}]
set_property MARK_DEBUG false [get_nets vp_IBUF]
connect_debug_port u_ila_0/probe2 [get_nets [list ready]]
connect_debug_port u_ila_0/clk [get_nets [list clk_IBUF_BUFG]]
connect_debug_port dbg_hub/clk [get_nets clk_IBUF_BUFG]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list your_instance_name/inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 16 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {adc_data[0]} {adc_data[1]} {adc_data[2]} {adc_data[3]} {adc_data[4]} {adc_data[5]} {adc_data[6]} {adc_data[7]} {adc_data[8]} {adc_data[9]} {adc_data[10]} {adc_data[11]} {adc_data[12]} {adc_data[13]} {adc_data[14]} {adc_data[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list den]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list drdy]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk50]
observation :
digital output waveform
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